A conventional semiconductor device will be described with reference to FIGS. 13, 14, and 15. FIG. 13 is a plan view illustrating a configuration of a chip in the conventional semiconductor device.
As illustrated in FIG. 13, pads 102 are arranged in an array on the principal surface of a chip 100 to be electrically connected to an internal circuit in the chip 100. Bumps 106 are respectively formed on the pads 102 with a barrier metal layer (not shown, and denoted by reference numeral 105 in FIG. 14) interposed therebetween.
FIG. 14 is a cross-sectional view illustrating the configuration of the chip in the conventional semiconductor device. Specifically, FIG. 14 is an enlarged cross-sectional view taken along line XIV-XIV in FIG. 13.
As illustrated in FIG. 14, the pads 102 are formed on an interlayer insulating film 100x. A first protective film 103 is formed over the interlayer insulating film 100x and the pads 102. The first protective film 103 has openings 103a in which the upper surfaces of the pads 102 are exposed. A second protective film 104 is formed on a region of the first protective film 103 except for a region on which the pads 102 are formed. The barrier metal layer 105 is formed on the pads 102 to fill the openings 103a. The bumps 106 are formed on the barrier metal layer 105.
FIG. 15 is a cross-sectional view illustrating a configuration of the conventional semiconductor device. Specifically, this cross-sectional view illustrates a configuration of the semiconductor device in which the chip with the configuration shown in FIG. 13 is mounted on the board. The cross-sectional view of the chip shown as the upper chip in FIG. 15 is the cross-sectional view taken along line XV-XV in FIG. 13.
As illustrated in FIG. 15, the chip 100 is connected to the board 200 having terminals 201 via the bumps 106. The gap between the board 200 and the chip 100 is filled with resin 202. In this manner, the chip 100 is mounted on the board 200.
The chip 100 and the board 200 greatly differ in thermal expansion coefficient. Thus, when thermal stress is applied to the pad 102-bump 106 portion sandwiched between the board 200 and the chip 100 in mounting the chip on the board, for example, reliability of the connection between the pad 102-bump 106 portion and the board 200 is reduced (see, for example, Japanese Patent Publication No. 8-153747).